Field of the Invention
The invention relates to a circuit configuration for triggering a power FET, with which a load is connected in series on the source side, having the following characteristics:
a) the gate electrode of the power FET is connected to a first input terminal through a first diode and a capacitor, PA0 b) a second diode is connected between the first diode and the capacitor and is connected through the drain-to-source path of a second FET with the drain terminal of the power FET, PA0 c) the second FET is of the opposite channel type from that of the power FET, PA0 d) a resistor is connected between the gate and source terminals of the second FET, PA0 e) the gate terminal of the second FET is connected to a controllable switch, and PA0 f) the gate-to-source capacitance of the power FET can be discharged through the drain-to-source path of a third FET.